Serially addressed integrated circuit memory devices are well known in the art. See, for example, U.S. Pat. Nos. 5,663,922 and 6,097,657. As shown in U.S. Pat. No. 5,663,922, it is well known in the art to decode a partial address received by a serially addressed integrated circuit memory device to activate and “read” various portions of the memory array. This mechanism of decoding the address signals as they are serially inputted increases the performance of such a device by reading as soon as possible those cells which are selected by the partial address. The shortcoming of U.S. Pat. No. 5,663,922 is that it does not address the problem of saving power; the '922 patent increases the total number of sense amplifiers and activates all of the sense amplifiers as the serial addresses is received and is decoded. As a result, the '922 patent does not teach an integrated circuit memory device with power saving as its consideration.
Similarly, U.S. Pat. No. 6,097,657 also does not teach activating the sensing amplifiers only after all the various addresses have been completed decoded thereby saving power to the sensing amplifier.
Accordingly, there is a need for an integrated circuit memory device that is rapid in that it decodes a partially received address in a serially addressed memory device as well as saving power in the operation of the memory device.